Silicon carbide wafers are widely used in power electronics, RF devices, high-temperature electronics and semiconductor research. However, two SiC wafers with the same diameter and thickness can perform very differently during epitaxy or device fabrication.

Crystal defects, surface damage, geometric variation, resistivity non-uniformity and contamination may all affect process yield and device reliability. Therefore, checking only the wafer diameter and surface appearance is not enough.

This guide explains the most important SiC wafer inspection items, how they are measured and what buyers should request from a supplier before approving a production lot.

What Determines SiC Wafer Quality?

SiC wafer quality is usually evaluated in five main areas:

1. Crystal structure and crystallographic defects
2. Wafer dimensions and geometry
3. Surface quality and roughness
4. Electrical properties and uniformity
5. Cleanliness, identification and traceability

The importance of each item depends on the intended application. A device-grade substrate prepared for epitaxial growth normally requires tighter controls than a research wafer, dummy wafer or equipment calibration wafer.

There is no single specification that defines a “good” SiC wafer for every application. The correct acceptance limits should be established according to the device process, wafer size, conductivity type and required production yield.

Quick Overview of Common SiC Wafer Inspection Items

1. Verify the SiC Polytype

Silicon carbide has many crystal structures, known as polytypes. The most common semiconductor grades are 4H-SiC and 6H-SiC.

Today, 4H-SiC is commonly selected for power devices because of its favorable carrier mobility, wide bandgap and high critical electric field. However, 6H-SiC may still be used for certain research, optical or specialized applications.

The polytype should be clearly stated on the certificate of analysis. Raman spectroscopy and X-ray diffraction can be used to confirm the crystal structure and identify possible polytype inclusions.

A buyer should not assume that all SiC wafers have the same crystal structure simply because they have the same color, diameter or conductivity type.

2. Check Crystal Orientation and Off-Axis Angle

Most commercial 4H-SiC substrates are produced with a defined crystallographic orientation, commonly based on the (0001) plane. The wafer may also have a specified off-axis angle and direction.

The off-axis orientation is particularly important for epitaxial growth. It supports step-flow growth and helps control the formation of undesirable crystal structures in the epitaxial layer.

Important orientation information may include:

• Crystal plane
• Si-face or C-face
• Off-axis angle
• Off-axis direction
• Orientation tolerance
• Primary flat or notch orientation

X-ray diffraction is commonly used to verify crystal orientation and offcut. When ordering wafers for epitaxy, the buyer should specify both the nominal off-axis angle and the acceptable tolerance.

3. Inspect Micropipes and Other Crystal Defects

Crystal defects are among the most important factors affecting SiC wafer quality.

Micropipes

A micropipe is a hollow-core defect associated with a large screw dislocation. It can pass through the substrate and interfere with epitaxial growth or device fabrication.

Micropipes were once a major limitation in SiC manufacturing. Although modern crystal growth has significantly reduced their density, micropipe inspection remains important for high-voltage and high-reliability applications.

Threading Screw Dislocations

Threading screw dislocations, or TSDs, extend approximately along the crystal growth direction. They may influence breakdown behavior, leakage current and device reliability.

Their effect depends on the device structure, location and process design. Therefore, both defect density and spatial distribution may be relevant.

Threading Edge Dislocations

Threading edge dislocations, or TEDs, are commonly found in SiC substrates. Although they may be less destructive than micropipes, high densities can still affect epitaxial quality and device performance.

Basal Plane Dislocations

Basal plane dislocations, or BPDs, are important in bipolar device applications because they can contribute to the formation or expansion of stacking faults under electrical stress.

For applications sensitive to bipolar degradation, BPD density and conversion behavior during epitaxy should be carefully evaluated.

Stacking Faults and Polytype Inclusions

Stacking faults are interruptions in the normal stacking sequence of the SiC crystal. Polytype inclusions are regions where an unintended SiC crystal structure is present.

Both defects can interfere with epitaxy and affect electrical performance.

Common defect inspection methods include:

• Photoluminescence mapping
• X-ray topography
• Optical microscopy
• Laser-scattering inspection
• Raman spectroscopy
• Molten KOH etching

Some methods are non-destructive, while chemical etching is destructive. Buyers should confirm which inspection method was used and whether the reported result represents the entire wafer or only sampled areas.

4. Measure Wafer Diameter and Thickness

Wafer diameter and thickness determine whether the substrate is compatible with processing, handling, polishing and epitaxy equipment.

Key dimensional items include:

• Nominal diameter
• Diameter tolerance
• Nominal thickness
• Thickness tolerance
• Edge profile
• Notch or flat dimensions

Thickness requirements may vary according to wafer diameter and intended use. A thinner wafer may be needed for a specific device process, while a thicker substrate may offer better mechanical stability during research or equipment testing.

For custom-thickness wafers, buyers should also evaluate whether additional grinding or polishing may increase bow, warp or subsurface damage.

5. Evaluate Total Thickness Variation

Total thickness variation, commonly abbreviated as TTV, is the difference between the maximum and minimum measured thickness across the wafer within a defined measurement area.

A low TTV is important because excessive thickness variation can affect:

• Lithography focus
• Wafer chucking
• Grinding and thinning uniformity
• Epitaxial process conditions
• Device layer thickness control
• Wafer bonding

TTV values can be influenced by the measurement method, number of measurement points and edge-exclusion area. Therefore, a specification should not state only a maximum TTV value. It should also identify the agreed measurement conditions.

6. Check Bow and Warp

Bow and warp describe the shape of a free, unclamped wafer, but they are not the same measurement.

Bow generally describes the deviation of the wafer’s median surface from a reference plane.

Warp represents the overall difference between the highest and lowest points of the median surface relative to a reference plane.

Excessive bow or warp can cause problems during:

• Automated wafer handling
• Vacuum chucking
• Lithography
• Epitaxial growth
• Wafer bonding
• Grinding and polishing
• Film deposition

Larger-diameter and thinner SiC wafers may be more sensitive to geometric deformation. Buyers should define the measurement method, edge exclusion and wafer support conditions when comparing data from different suppliers.

7. Inspect Surface Roughness

An epitaxy-ready SiC surface must be extremely smooth and free from significant polishing damage.

Atomic force microscopy, or AFM, is commonly used to measure root mean square surface roughness. However, the reported value depends strongly on the scan area, instrument settings and measurement location.

A roughness result should therefore include:

• RMS or Ra value
• AFM scan size
• Number of tested locations
• Measurement surface
• Edge-exclusion condition

A single roughness value without a scan size or sampling plan is difficult to compare.

For wafers intended for epitaxy, surface quality should also be evaluated for polishing-related defects such as scratches, pits, residual subsurface damage and step bunching.

8. Examine Scratches, Pits and Surface Defects

A wafer may look clean to the naked eye while still containing defects that affect epitaxial growth or device fabrication.

Common surface defects include:

• Scratches
• Pits
• Dents
• Stains
• Haze
• Particles
• Edge chips
• Polishing marks
• Orange-peel texture
• Subsurface damage

Inspection can be performed using bright-field microscopy, dark-field microscopy, laser-scattering systems and automated surface scanners.

The acceptance criteria should define the minimum detectable defect size, allowable defect count and edge-exclusion area. Descriptions such as “mirror polished” or “scratch-free” are not sufficient unless accompanied by measurable standards.

9. Confirm Si-Face, C-Face and Surface Finish

SiC wafers have two polar surfaces: the silicon-terminated face and the carbon-terminated face. These surfaces do not behave identically during oxidation, etching, polishing or epitaxy.

The supplier should identify:

• Which side is the Si-face
• Which side is the C-face
• Which side is epi-ready
• Whether the wafer is single-side polished or double-side polished
• Backside roughness or finish
• Front-side identification method

Incorrect face identification can lead to process failure, especially during epitaxial growth or surface research.

For single-side polished wafers, the buyer should also confirm whether the backside is fine-ground, etched, lapped or polished.

10. Evaluate Resistivity and Doping Uniformity

Electrical performance is another essential part of SiC wafer quality.

Conductive N-type SiC wafers are commonly nitrogen doped. Other doping types and semi-insulating grades are also available for specialized applications.

Important electrical parameters may include:

• Conductivity type
• Dopant
• Resistivity range
• Resistivity uniformity
• Carrier concentration
• Carrier mobility
• Radial and axial uniformity

Four-point probe testing, contactless resistivity measurement, eddy-current mapping and Hall-effect measurement may be used depending on the wafer type and resistance range.

An average resistivity value alone may not be enough. For device manufacturing, the variation from the wafer center to the edge and from wafer to wafer within the same lot can be equally important.

For semi-insulating SiC wafers, the measurement method must be suitable for high-resistivity material. The supplier should state the test temperature, measurement range and acceptance criteria.

11. Check Surface Contamination and Particle Levels

Metallic contamination, organic residues and particles can reduce epitaxial and device yield even when the wafer meets its geometric specifications.

Possible inspection techniques include:

• Automated particle scanning
• Total reflection X-ray fluorescence
• X-ray photoelectron spectroscopy
• Secondary ion mass spectrometry
• Surface ion or chemical analysis

Not every order requires advanced contamination testing. However, buyers should at least confirm the wafer cleaning process, final packaging environment and maximum allowable particle level when the material is intended for sensitive semiconductor fabrication.

12. Inspect the Wafer Edge, Flat or Notch

The wafer edge affects mechanical strength and automated handling.

Inspect the edge for:

• Chips
• Cracks
• Bevel defects
• Uneven edge profiles
• Incorrect notch or flat dimensions
• Incorrect orientation-mark position

Small edge defects may grow during high-temperature processing, grinding or wafer transport. For this reason, edge inspection should be included in incoming quality control, especially for thin or large-diameter wafers.

The position and dimensions of the primary flat or notch should also match the processing equipment and crystallographic orientation requirements.

13. Review the Wafer Map, COA and Lot Traceability

A complete certificate of analysis should clearly link the inspection results to the supplied wafer or production lot.

Depending on the order, useful documentation may include:

• Unique wafer identification number
• Lot and crystal-boule number
• Polytype and orientation
• Diameter and thickness
• TTV, bow and warp
• Surface roughness
• Conductivity type and resistivity
• Micropipe or dislocation data
• Surface defect results
• Inspection date and method
• Wafer-level defect or resistivity maps
• Packaging and cleaning information

A lot-level average cannot always reveal local defects or wafer-to-wafer variation. For critical applications, request individual wafer data or wafer maps rather than relying only on a general batch certificate.

Traceability is also important when comparing epitaxial results, identifying process problems or evaluating long-term supplier consistency.

Substrate Inspection Is Different from Epitaxial Wafer Inspection

A bare SiC substrate and an epitaxial SiC wafer require different inspection plans.

In addition to substrate parameters, an epitaxial wafer may require evaluation of:

• Epitaxial layer thickness
• Thickness uniformity
• Doping concentration
• Doping uniformity
• Surface morphology
• Epitaxial defect density
• Carrier lifetime
• Step bunching
• Triangular defects
• Downfall particles
• Basal plane dislocation conversion

Buyers should clearly state whether they require a polished substrate, an epi-ready substrate or a wafer with an epitaxial layer.

How to Perform Incoming Inspection

A practical incoming inspection process can be divided into four steps.

Step 1: Verify Documentation

Confirm that the wafer identification, purchase order, packaging label and COA refer to the same wafer or lot.

Step 2: Perform Visual and Dimensional Inspection

Check diameter, thickness, edge condition, surface identification and visible scratches, particles or chips.

Step 3: Measure Critical Parameters

Measure the properties most relevant to the process, such as TTV, bow, warp, roughness or resistivity.

Step 4: Compare Results with Wafer Maps and Process Performance

For production use, correlate incoming inspection data with epitaxial defects, fabrication yield and final device performance. This helps determine which substrate parameters have the greatest effect on the actual process.

SiC Wafer RFQ Checklist

Before requesting a quotation, provide the following information:

• Application or intended process
• SiC polytype: 4H-SiC, 6H-SiC or another type
• Wafer diameter
• Crystal orientation
• Off-axis angle and direction
• Si-face or C-face requirement
• Conductive or semi-insulating grade
• Conductivity type and dopant
• Resistivity range and uniformity
• Nominal thickness and tolerance
• Maximum TTV, bow and warp
• Single-side or double-side polishing
• Surface roughness requirement
• Allowed crystal and surface defect levels
• Edge, flat or notch requirements
• Cleaning and packaging requirements
• COA, wafer map and traceability requirements
• Required quantity

Providing a complete specification reduces technical clarification time and helps the supplier select the correct wafer grade.

Frequently Asked Questions

What is the most important SiC wafer quality parameter?

There is no single most important parameter for every application. Crystal defects, surface condition, geometry and resistivity must be considered together. For epitaxy, the off-axis angle, surface roughness, subsurface damage and crystal defects are often especially important.

Is a lower TTV always better?

A lower TTV generally improves process uniformity, but tighter specifications may increase manufacturing cost. The correct limit should be based on the equipment, lithography process, bonding method and final device requirements.

Can visual inspection detect all SiC wafer defects?

No. Visual inspection may identify scratches, chips, stains and large surface defects, but it cannot reveal all subsurface or crystallographic defects. PL mapping, X-ray topography, AFM and other analytical methods may be required.

Why is AFM scan size important?

Surface roughness can appear different when measured over different scan areas. An AFM result should always include the scan size, measurement location and number of sampled points.

What is the difference between research-grade and device-grade SiC wafers?

Research-grade wafers may have wider tolerances or higher allowable defect levels. Device-grade or epi-ready wafers generally require tighter control of crystal defects, surface condition, geometry, resistivity and traceability.

Should buyers request a wafer-level inspection map?

A wafer-level map is recommended for applications where defect position, resistivity uniformity or local surface conditions can affect device yield. It provides more useful information than a single lot-average value.

Conclusion

Evaluating SiC wafer quality requires more than checking diameter, thickness and visual appearance. Crystal structure, dislocation density, TTV, bow, warp, surface roughness, resistivity, contamination and traceability can all influence epitaxial growth and device yield.

The first step is to define the wafer’s intended application. Buyers can then establish measurable acceptance criteria and request inspection results based on the parameters that directly affect their process.

When requesting a quotation, provide the polytype, diameter, orientation, conductivity, thickness, geometric tolerances, surface requirements and documentation needs. A detailed RFQ makes it easier to compare wafers accurately and avoid receiving material that meets a general description but does not match the actual application.