As silicon carbide manufacturing moves toward larger wafer diameters, edge quality becomes increasingly important. For a 200 mm SiC wafer, it is not sufficient to evaluate only diameter, thickness, TTV, bow, warp and surface roughness. The condition of the wafer perimeter can directly affect handling stability, epitaxial processing, cleaning, lithography, wafer thinning and downstream device yield.

A wafer may have an excellent polished central surface while still containing edge chips, microcracks or subsurface damage around the bevel. These defects can become particle sources or mechanical failure initiation points during later processing.

For this reason, buyers of 200 mm SiC substrates should include bevel geometry, edge exclusion, edge chipping limits and edge inspection requirements in the wafer specification rather than treating the edge as a secondary characteristic.

Why Edge Quality Becomes More Important at 200 mm

Increasing wafer diameter improves the number of devices that can be processed per wafer, but it also increases the mechanical and process-control requirements placed on the substrate.

A 200 mm SiC wafer must pass through multiple automated systems, including:

• Wafer cassettes and FOUP-compatible handling
• Robotic wafer transfer
• Cleaning equipment
• Epitaxy reactors
• Inspection systems
• Backgrinding and thinning equipment
• Lithography and coating processes

During these operations, the wafer edge experiences repeated mechanical contact and thermal cycling.

Even relatively small edge defects can therefore become important.

Typical edge-related risks include:

• Local chipping
• Radial microcracks
• Bevel scratches
• Sharp edge transitions
• Subsurface cracks
• Loose particles
• Edge contamination
• Irregular edge geometry

SEMI's work on polished monocrystalline SiC wafer specifications has specifically included physical characteristics such as edge shape, flatness, orientation and defects as the industry has moved toward 200 mm substrates.

1. Bevel Geometry

The outer perimeter of a semiconductor wafer is normally shaped rather than left as a sharp 90-degree corner.

This shaped region is commonly referred to as the bevel, edge profile or edge contour.

The purpose of edge shaping is to reduce mechanical stress concentration and make the wafer more resistant to chipping during handling and processing.

SEMI's wafer-edge contour test methodology notes that contouring the edge helps reduce chipping and can also reduce problems such as epitaxial edge crown and photoresist edge bead.

For SiC wafers, bevel geometry is especially important because SiC is extremely hard but comparatively brittle during mechanical machining.

Important Bevel Parameters

A wafer purchase specification may need to define:

• Bevel width
• Edge radius
• Bevel angle
• Front-side transition
• Back-side transition
• Edge symmetry
• Edge profile consistency
• Notch geometry
• Bevel surface finish

There is no single bevel geometry that is ideal for every process.

The appropriate profile depends on factors such as:

• Final wafer thickness
• Epitaxy requirements
• Chuck design
• Wafer handling method
• Planned backgrinding
• Device edge exclusion
• Automation compatibility

For this reason, sophisticated buyers should avoid specifying only "standard bevel."

Where edge geometry is critical, an agreed edge profile drawing or inspection method should be included in the purchase specification.

2. Edge Exclusion

Edge exclusion (EE) defines the peripheral region of the wafer that is excluded from certain surface or geometry requirements.

In SEMI terminology, edge exclusion is essentially the distance between the boundary of the fixed quality area and the nominal wafer perimeter.

This distinction is important because wafer properties often change near the edge.

Examples include:

• Local thickness variation
• Surface roll-off
• Edge polishing marks
• Particle concentration
• Epitaxial thickness variation
• Resist coating non-uniformity
• Edge bead
• Local surface defects

Consequently, a buyer should not simply specify:

TTV ≤ X µm

A more complete specification should clarify where TTV is measured and what edge exclusion is applied.

The same principle applies to:

• Flatness
• Bow
• Warp
• Surface roughness
• Particle inspection
• Defect inspection
• Epitaxial thickness uniformity

Near-edge geometry has become important enough that SEMI M67 defines specialized metrics such as ESFQR, ESFQD and ESBIR for evaluating wafer geometry close to the perimeter.

3. Edge Chipping

Edge chipping is one of the most visible wafer-edge defects.

It can occur during:

• Crystal slicing
• Edge grinding
• Lapping
• Polishing
• Cleaning
• Wafer transport
• Cassette loading
• Backgrinding
• Mechanical handling

A chip may initially appear to be only a cosmetic defect, but its significance depends on its depth, width, location and whether a crack extends from the chipped region.

For production wafers, buyers should therefore avoid specifications such as:

No serious edge chipping.

This wording is difficult to inspect objectively.

A better RFQ should define measurable acceptance criteria, such as:

• Maximum chip width
• Maximum chip depth
• Maximum number of chips
• Whether chips may enter the polished surface
• Whether radial cracks are permitted
• Inspection magnification
• Critical versus non-critical edge regions

Why Small Chips Can Matter

A damaged edge can become a stress-concentration point.

During subsequent thermal or mechanical loading, an existing crack can extend further into the wafer.

The risk becomes particularly important during:

• High-temperature epitaxy
• Rapid thermal processing
• Wafer thinning
• Dicing
• Wafer bonding
• Automated high-speed handling

The safest approach is therefore to evaluate both the visible chip and the possibility of associated microcracking.

4. Subsurface Damage Around the SiC Edge

One of the more difficult quality problems is subsurface damage, or SSD.

A wafer edge can appear smooth under normal visual inspection while damaged material remains beneath the surface.

SiC machining research has shown that grinding can produce damage modes including chipping pits and subsurface lateral or median cracks. Research on 4H-SiC has also demonstrated that grinding and polishing can leave nanoscale subsurface damage that is not fully represented by ordinary surface roughness measurements.

Potential forms of SSD include:

• Microcracks
• Residual mechanical stress
• Crystal lattice damage
• Dislocations
• Local fractured regions

What Causes SSD?

Important variables include:

• Grinding wheel grit size
• Feed rate
• Grinding pressure
• Wheel speed
• Material removal depth
• Cooling conditions
• Polishing process
• CMP removal depth

Coarser or more aggressive mechanical processing generally creates a deeper damage layer that must subsequently be removed or reduced.

This is why a mirror-like appearance alone cannot prove that the wafer edge has excellent mechanical integrity.

5. Edge Quality and Epitaxial Processing

Edge quality becomes especially important when a SiC substrate will be used for homoepitaxial growth.

Poor edge geometry can contribute to process complications near the wafer perimeter, including:

• Edge crown
• Local epitaxial thickness variation
• Particle formation
• Non-uniform gas-flow effects
• Edge defect propagation

The device manufacturer may intentionally exclude part of the wafer perimeter from the usable device area, but excessive edge damage can extend beyond the planned exclusion zone.

For an epitaxy-ready SiC substrate, the RFQ should therefore consider the relationship between:

physical bevel → edge exclusion → usable area → epitaxial exclusion → device yield

rather than treating these items independently.

6. Incoming Inspection for 200 mm SiC Wafers

For high-value 200 mm SiC substrates, incoming inspection should use a structured sequence.

Step 1: Packaging Inspection

Before opening the wafer container, inspect:

• Shipping box condition
• Shock or impact signs
• Moisture protection
• Cassette or wafer box condition
• Wafer movement inside the carrier

This helps distinguish transportation damage from manufacturing defects.

Step 2: Wafer Identification

Confirm:

• Diameter
• Thickness
• Conductivity type
• Crystal orientation
• Off-axis angle
• Si-face / C-face
• Lot number
• Wafer ID

Traceability becomes particularly important when edge damage is found repeatedly within the same manufacturing lot.

Step 3: Visual Edge Inspection

Inspect the complete circumference for:

• Chips
• Cracks
• Scratches
• Stains
• Residues
• Edge particles
• Abnormal bevel geometry

Inspection conditions should be standardized.

Step 4: Magnified Edge Inspection

Optical magnification can be used where smaller defects must be detected.

Special attention should be paid to:

• Chip boundaries
• Radial cracks
• Notch area
• Front-bevel transition
• Back-bevel transition

The notch region deserves particular attention because local geometry is different from the circular wafer perimeter.

Step 5: Edge Profile Measurement

Where required, measure:

• Bevel geometry
• Edge contour
• Edge symmetry
• Edge roll-off
• Transition geometry

SEMI M73 provides a methodology for extracting characteristics from measured wafer edge profiles, reflecting the increasing importance of quantitatively controlling edge shape in advanced wafer processing.

Step 6: Geometry Inspection

The inspection report should also include the agreed wafer geometry parameters, such as:

• Thickness
• TTV
• Bow
• Warp
• Global flatness
• Near-edge flatness

Near-edge geometry should not automatically be assumed to behave identically to the central wafer area.

Step 7: Surface and Particle Inspection

Finally, inspect the relationship between the bevel and polished wafer surface.

Check for:

• Particles released from edge damage
• Polishing residue
• Edge contamination
• Scratches entering the active area
• Surface defects originating near the edge

7. Recommended RFQ Items for 200 mm SiC Wafers

A practical RFQ can contain the following items:

The exact acceptance values should be agreed between supplier and customer because device processes and metrology systems are different.

8. Questions to Ask a SiC Wafer Supplier

Before purchasing 200 mm substrates, buyers may ask:

1. What bevel geometry is used for the 200 mm wafer?
2. Can you provide an edge profile drawing?
3. What edge exclusion is used for TTV and surface inspection?
4. How is edge chipping measured?
5. Are radial edge cracks included in the rejection criteria?
6. What inspection magnification is used?
7. Is the notch inspected separately?
8. Can near-edge geometry data be provided?
9. Is an inspection report supplied with each lot?
10. Can custom edge specifications be supported?

These questions are often more useful than simply requesting a generic "prime-grade" wafer.

Conclusion

As SiC manufacturing advances toward 200 mm production, wafer-edge quality becomes an important part of substrate qualification.

The central polished surface may receive most of the attention, but bevel geometry, edge exclusion, chipping and hidden subsurface damage can influence handling reliability, epitaxial processing, contamination control and usable wafer area.

For procurement teams, the key is to replace vague requirements such as "good edge quality" with measurable specifications.

A complete 200 mm SiC wafer RFQ should therefore define:

bevel geometry + edge exclusion + chipping criteria + crack acceptance + inspection method + wafer geometry + reporting requirements.

Clear edge specifications make it easier for both the wafer supplier and device manufacturer to establish consistent incoming inspection criteria and reduce disputes during production qualification.

FAQ

What is edge exclusion on a SiC wafer?

Edge exclusion is the peripheral region between the wafer edge and the boundary of the area used for specified measurements or quality evaluation. It should be clearly defined when specifying flatness, defects, particles or epitaxial uniformity.

Why is bevel geometry important for 200 mm SiC wafers?

A properly controlled bevel reduces sharp-edge stress concentration and helps limit chipping during handling. It can also affect near-edge processing behavior during epitaxy, coating, cleaning and lithography.

Can a SiC wafer pass visual inspection but still contain edge damage?

Yes. Microcracks and subsurface damage may remain below a visually smooth surface. For demanding applications, magnified inspection and suitable process or metrology controls may be required.